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NEW QUESTION: 1
When microcomputers were first developed, the instruction fetch time
was much longer than the instruction execution time because of the
relatively slow speed of memory accesses. This situation led to the
design of the:
A. Very-Long-Instruction-Word (VLIW) processor
B. Complex Instruction Set Computer (CISC)
C. Superscalar processor
D. Reduced Instruction Set Computer (RISC)
Answer: B
Explanation:
The logic was that since it took a long time to fetch an instruction
from memory relative to the time required to execute that
instruction in the CPU, then the number of instructions required to
implement a program should be reduced. This reasoning naturally
resulted in densely coded instructions with more decode and
execution cycles in the processor. This situation was ameliorated by
pipelining the instructions wherein the decode and execution cycles
of one instruction would be overlapped in time with the fetch cycle
of the next instruction.
* Answer "Reduced Instruction Set Computer (RISC)", RISC, evolved when packaging and memory technology advanced to the point where there was not much difference in memory access times and processor execution
times. Thus, the objective of the RISC architecture was to reduce the
number of cycles required to execute an instruction. Accordingly,
this increased the number of instructions in the average program by
approximately 30%, but it reduced the number of cycles per
instruction on the average by a factor of four. Essentially, the RISC
architecture uses simpler instructions but makes use of other
features such as optimizing compilers to reduce the number of
instructions required and large numbers of general purpose registers
in the processor and data caches.
* The superscalar processor, answer "Superscalar processor",
allows concurrent execution of instructions in the same pipelined
stage. A scalar processor is defined as a processor that executes one
instruction at a time. The term superscalar denotes multiple,
concurrent operations performed on scalar values as opposed to
vectors or arrays that are used as objects of computation in array
processors.
* For answer "Very-Long-Instruction-Word (VLIW) processor" multiple, concurrent operations are performed in a single instruction. Because multiple operations are performed in one
instruction rather than using multiple instructions, the number of
instructions is reduced relative to those in a scalar processor.
However, for this approach to be feasible, the operations in each
VLIW instruction must be independent of each other.
NEW QUESTION: 2
DRAG DROP
A company plans to use operations management suite (OMS) to track changes within virtual machines (VMs).
You need to determine the change types that report differences when changes are found.
Which action for which source types is performed by the OMS agent? To answer, drag the appropriate action to the data source.
Each action may be use once, more than once, or not at all. You may need to drag the split bar between panes or scroll to view contain.
NOTE: Each correct selection is worth one point.
Answer:
Explanation:
NEW QUESTION: 3
What influence does the checking horizon have for demands which cannot be confirmed in time?
A. Based on lot size procedure, the remaining quantity can be confirmed after the dynamically calculated checking horizon.
B. At the end of the checking horizon, the total demand quantities can be automatically confirmed.
C. At the end of the checking horizon, the remaining quantity automatically creates a planned receipt.
D. At the end of the checking horizon, the remaining quantities have to be confirmed manually.
Answer: B